搜索资源列表
firfilter
- fir滤波 基于fpga 的 三阶滤波-fir filter third-order filter on fpga
weitb
- 在数字通信中,通常直接从接收到的数字信号中提取位同步信号,这种直接法按其提取同步信号的方式,大致可分为滤波法和锁相法。锁相法是指利用锁相环来提取位同步信号的方法,本设计方案就是基于锁相环的位同步提取方法,能够比较快速地提取位同步时钟,并且设计简单,方便修改参数。采用Quartus II设计软件对系统进行了仿真试验,并用Altera的Cyclone II系列FPGA芯片Ep2c5予以实现。-In digital communication, usually from receiving direc
zzlB
- QUARTUSII 9.0 下的三级流水线中值滤波工程,vhdl源程序等。可用于fpga做图像预处理。-the three stage pipeline median filter project under QUARTUSII 9 , VHDL source program. which can be used by FPGA to do image preprocessing.
DDS_fir
- FFR滤波器在FPGA上的硬件实现,及检测!可以检测AD输入模块的滤波状况-FFR filter FPGA realize, can detect AD input data filtering effect
all_MedFilter_VHDL
- 本文介绍了中值滤波算法的FPGA详细实现,很详细,很全-This article describes the median filter algorithm to achieve the FPGA detailed, very detailed, very full
sift-1.1.2_20101207_win
- 包含高斯滤波和sift的FPGA中VHDL代码,相信对做硬件的各位很有用的-FPGA,sift,VHDL code
DBS-design
- 多普勒波束锐化,方位高分辨滤波器设计,】在详细分析多普勒波束锐化(DBS)方位高分辨率实现的基础上.提出能够保持近似 恒定锐化比的新预处理滤波算法。给出了基于FPGA的具体算法实现,-DBS;high azimuth resolutionf filter design,radar seeker
key_scan
- 这个是学习FPGA时候自己写的键盘扫描的代码。采用的是边沿检测的方法,并且进行了滤波处理,本人测试仿真成功!-This is when the FPGA write their own learning keyboard scan code. Use is edge detection method, and its filtering processing, I test simulation success!
dintlace
- 功能超强的视频信号隔行转逐行的滤波verilog代码,经过fpga验证。-The function of super-interlaced video signal transfer progressive filter Verilog code, after the fpga verification.
april2010_1
- 基于FPGA的方向滤波指纹图像增强算法实现,本文利用FPGA具有丰富寄存器资源、可满足高速系统设计等特点,设计了一种基于FPGA纯硬件方式实现方向滤波的指纹图像增强算法。设计采用寄存器传输级(RTL)硬件描述语言(Verilog HDL),利用时分复用和流水线处理等技术,完成了方向滤波指纹图像增强算法在FPGA上的实现。-Directional filtering fingerprint image enhancement algorithm based on FPGA using the FP
tsobbellh
- 这是我本人自己开发的可用于256*256大小的图像进行sobel边缘检测的vhd文件,可在QuartusII或MaxplisII下综合与与仿真,并在FPGA上测试过。能进行修改支持其他大小图像的sobeel边缘检测,同时还能实现其它的图像模块化处理算法,例如高斯滤波,平滑等。 -This is my own development vhd file, can be used for 256* 256 size image sobel edge detection under QuartusI
signal-fir
- FPGA实现FIR滤波器,对信号的滤波处理,其中I用IP核实现数据的存储核-Based on the IP core of FPG, realize FIR filter design
tss_filterh
- fpga实现图象滤波,实时的实现现对输入图象的形态学滤波可直接使用。 -fpga image filtering, real-time implementations currently morphological filtering of the input image can be used directly.
Pro_19
- Fpga,DDS,PLL,rom(正弦波)(f<13MHz,需要滤波)(Verilog)-Fpga, DDS, PLL, rom
HalfbandDec
- 基于FPGA开发的11阶半带升余弦FIR滤波器,用在阅读器基带滤波时的抽取滤波器使用,采用verilog语言实现。-Raised cosine FIR filter based FPGA development 11 order of half-band decimation filter used in reader baseband filtering, using verilog language implementation.
rc_flt
- 基于FPGA实现的64阶升余弦FIR并行滤波器,采用iso18000.6c标准实现,具有很好的低通滤波效果,已通过后仿上板验证,采用verilog语言实现。-64 order raised cosine FIR FPGA-based parallel filters, implemented using iso18000.6c standard with a low-pass filtering effect imitation on the board has passed validatio
FilterMid
- FPGA实现的图像中植滤波算法,硬件平台DE2开发板-Vegetation filtering algorithms, hardware platforms DE2 development board FPGA implementation of image
image-processing
- 图像处理方面,使用Altera公司的stratix系列的FPGA对图像进行高通滤波和高斯滤波-Image processing, Altera Corporation stratix series FPGA high-pass filter and Gaussian filter image
fir
- 基于FPGA的低通滤波器的设计,仿真环境是QuartusII9.0。对信号进行低通滤波,编程成功。希望对大家有所帮助-FPGA-based low-pass filter design, the simulation environment QuartusII9.0. The signal is low-pass filtering, the programming was successful. We hope to help
Midian_fpga
- 图像处理中用到的中值滤波,FPGA实现。verilog语言。-Used in image processing median filter, FPGA implementation. verilog language.